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120 mA, Current Sinking, 10-Bit, I2C(R) DAC AD5821
FEATURES
120 mA current sink Available in 3 x 3 array WLCSP package 2-wire (I2C-compatible) 1.8 V serial interface 10-bit resolution Integrated current sense resistor 2.7 V to 5.5 V power supply Guaranteed monotonic over all codes Power-down to 0.5 A typical Internal reference Ultralow noise preamplifier Power-down function Power-on reset
INDUSTRIAL APPLICATIONS
Heater controls Fan controls Cooler (Peltier) controls Solenoid controls Valve controls Linear actuator controls Light controls Current loop controls
GENERAL DESCRIPTION
The AD5821 is a single 10-bit digital-to-analog converter with 120 mA output current sink capability. It features an internal reference and operates from a single 2.7 V to 5.5 V supply. The DAC is controlled via a 2-wire (I2C-compatible) serial interface that operates at clock rates up to 400 kHz. The AD5821 incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V and remains there until a valid write takes place. It has a power-down feature that reduces the current consumption of the device to 1 A maximum. The AD5821 is designed for autofocus, image stabilization, and optical zoom applications in camera phones, digital still cameras, and camcorders. The AD5821 also has many industrial applications, such as controlling temperature, light, and movement, over the range of -40C to +85C without derating. The I2C address for the AD5821 is 0x18.
CONSUMER APPLICATIONS
Lens autofocus Image stabilization Optical zoom Shutters Iris/exposure Neutral density (ND) filters Lens covers Camera phones Digital still cameras Camera modules Digital video cameras/camcorders Camera-enabled devices Security cameras Web/PC cameras
FUNCTIONAL BLOCK DIAGRAM
XSHUTDOWN REFERENCE POWER-ON RESET SDA SCL I2C SERIAL INTERFACE 10-BIT CURRENT OUTPUT DAC VDD D1 ISINK VDD DGND
R
AD5821
DGND
RSENSE 3.3
05950-001
AGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD5821 TABLE OF CONTENTS
Features .............................................................................................. 1 Consumer Applications ................................................................... 1 Industrial Applications .................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ..............................................7 Terminology .................................................................................... 10 Theory of Operation ...................................................................... 11 Serial Interface ............................................................................ 11 I2C Bus Operation ...................................................................... 11 Data Format ................................................................................ 11 Power Supply Bypassing and Grounding................................ 12 Applications Information .............................................................. 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
1/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD5821 SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 connected to VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DC PERFORMANCE Resolution Relative Accuracy 2 Differential Nonlinearity2, 3 Zero-Code Error2, 4 Offset Error @ Code 162 Gain Error2 Offset Error Drift4, 5 Gain Error Drift2, 5 OUTPUT CHARACTERISTICS Minimum Sink Current4 Maximum Sink Current Output Current During XSHUTDOWN Output Compliance5 Output Compliance5 Power-Up Time LOGIC INPUTS (XSHUTDOWN)5 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance LOGIC INPUTS (SCL, SDA)5 Input Low Voltage, VINL Input High Voltage, VINH Input Low Voltage, VINL Input High Voltage, VINH Input Leakage Current, IIN Input Hysteresis, VHYST Digital Input Capacitance, CIN Glitch Rejection 6 POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 2.7 V to 3.6 V IDD (Power-Down Mode) 7
1 2
Min
B Version 1 Typ Max
Unit
10 1.5 0 1 0.5 10 0.2 3 120 80 0.6 0.48 20
4 1 5 0.6 0.5
Bits LSB LSB mA mA % of FSR A/C LSB/C mA mA nA V V s
Test Conditions/Comments VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V with reduced performance 117 A/LSB Guaranteed monotonic over all codes All 0s loaded to DAC @ 25C
VDD VDD
XSHUTDOWN = 0 Output voltage range over which maximum 120 mA sink current is available Output voltage range over which 90 mA sink current is available To 10% of FS, coming out of power-down mode; VDD = 5 V
1 0.54 1.3 3 -0.3 1.26 -0.3 1.4 0.05 VDD 6 50 2.7 2.5 0.5 5.5 4 +0.54 VDD + 0.3 +0.54 VDD + 0.3 1
A V V pF V V V V A V pF ns V mA A
VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 3.6 V VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V VDD = 3.6 V to 5.5 V VIN = 0 V to VDD
Pulse width of spike suppressed
IDD specification is valid for all DAC codes VINH = 1.8 V, VINL = GND, VDD = 3.6 V VINH = 1.8 V, VINL = GND
Temperature range is as follows: B Version = -30C to +85C. See the Terminology section. 3 Linearity is tested using a reduced code range: Code 32 to Code 1023. 4 To achieve near zero output current, use the power-down feature. 5 Guaranteed by design and characterization; not production tested. XSHUTDOWN is active low. SDA and SCL pull-up resistors are tied to 1.8 V. 6 Input filtering on both the SCL and the SDA inputs suppresses noise spikes that are less than 50 ns. 7 XSHUTDOWN is active low.
Rev. 0 | Page 3 of 16
AD5821
AC SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 connected to VDD, unless otherwise noted. Table 2.
Parameter Output Current Settling Time Slew Rate Major Code Change Glitch Impulse Digital Feedthrough 3
1 2 3
B Version 1, 2 Min Typ Max 250 0.3 0.15 0.06
Unit s mA/s nA-s nA-s
Test Conditions/Comments VDD = 3.6 V, RL = 25 , LL = 680 H, 1/4 scale to 3/4 scale change (0x100 to 0x300) 1 LSB change around major carry
Temperature range is as follows: B Version = -40C to +85C. Guaranteed by design and characterization; not production tested. See the Terminology section.
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter 1 fSCL t1 t2 t3 t4 t5 t6 2 t7 t8 t9 t10 t11 B Version Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 250 300 20 + 0.1 CB 3 400 Unit kHz max s min s min s min s min ns min s max s min s min s min s min ns max ns min ns max ns max ns min pF max Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus free time between a stop condition and a start condition tR, rise time of both SCL and SDA when receiving May be CMOS driven tF, fall time of SDA when receiving tF, fall time of both SCL and SDA when transmitting Capacitive load for each bus line
CB
1 2 3
Guaranteed by design and characterization; not production tested. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VINH MIN of the SCL signal) to bridge the undefined region of the SCL falling edge. CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
Timing Diagram
SDA
t9
t3
t10
t11
t4
SCL
START CONDITION
REPEATED START CONDITION
STOP CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. 0 | Page 4 of 16
05950-002
t4
t6
t2
t5
t7
t1
t8
AD5821 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to AGND VDD to DGND AGND to DGND SCL, SDA to DGND XSHUTDOWN to DGND ISINK to AGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature (TJ MAX) WLFCSP Power Dissipation JA Thermal Impedance 1 Mounted on 4-Layer Board Lead Temperature, Soldering Maximum Peak Reflow Temperature 2
1
Rating -0.3 V to +5.5 V -0.3 V to VDD + 0.3 V -0.3 V to +0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -30C to +85C -65C to +150C 150C (TJ MAX - TA)/JA 95C/W 260C (5C)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
To achieve the optimum JA, it is recommended that the AD5821 be soldered on a 4-layer board. 2 As per JEDEC J-STD-020C.
Rev. 0 | Page 5 of 16
AD5821 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
3 2 1 A
B
VIEW FROM BALL SIDE
Figure 3. 9-Ball WLCSP Pin Configuration
Table 5. 9-Ball WLCSP Pin Function Description
Ball Number A1 A2 A3 B1 B2 B3 C1 C2 C3 Mnemonic ISINK NC XSHUTDOWN AGND DGND SDA DGND VDD SCL Description Output Current Sink. No Connection. Power-Down. Asynchronous power-down signal, active low. Analog Ground Pin. Digital Ground Pin. I2C Interface Signal. Digital Ground Pin. Digital Supply Voltage. I2C Interface Signal.
1515m NC XSHUTDOWN 1 ISINK 8
05950-021
C
DGND 2 1690m SDA 3
AGND 7
VDD 6
SCL 4
DGND 5
05950-030
Figure 4. Metallization Photo Dimensions shown in microns (m)
Rev. 0 | Page 6 of 16
AD5821 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 INL VDD = 3.8V TEMP = 25C 1.5
VERT = 50s/DIV
INL (LSB)
1.0
0.5
3
0
05034-004
HORIZ = 468A/DIV CH3 M50.0s
112
168
224
280
336
392
448
504
560
616
672
728
784
840
896
952
CODE
Figure 5. Typical INL vs. Code Plot
0.6 0.5 0.4 0.3 DNL (LSB) 0.2 0.1 0 -0.1
05034-005
1008 1023
56
0
-0.5
Figure 8. Settling Time for a 4-LSB Step (VDD = 3.6 V)
DNL VDD = 3.8V TEMP = 25C
VERT = 2A/DIV
4.8A p-p
1
-0.2 -0.3
HORIZ = 2s/DIV CH1 M2.0s
CODE
1008 1023
56
112
168
224
280
336
392
448
504
560
616
672
728
784
840
896
952
0
Figure 6. Typical DNL vs. Code Plot
92.0 91.5 91.0 90.5 90.0 89.5 89.0
05034-006
Figure 9. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V)
0.14 IOUT @ +25C 0.12 IOUT @ -40C 0.10 0.08 0.06 0.04 0.02 0 IOUT @ +85C
OUTPUT CURRENT (mA)
112
168
224
280
336
392
448
504
560
616
672
728
784
840
896
952
CODE
Figure 7. 1/4 to 3/4 Scale Settling Time (VDD = 3.6 V)
Figure 10. Sink Current vs. Code vs. Temperature (VDD = 3.6 V)
Rev. 0 | Page 7 of 16
1008 1023
88.0 53.5-6
100.0-6
150.0-6
200.0-6 TIME
250.0-6
300.0-6 333.1-6
0
56
05034-009
88.5
IOUT (A)
05034-008
05034-007
AD5821
2000 1800 1600 1400 1200
A/V
0.45 VDD = 3.6V 0.40 0.35 ZERO-CODE ERROR (mA) 0.30 0.25 0.20 0.15 0.10
05950-013
VDD = 4.5V
VDD = 3.8V
1000 800 600 400 200 0 10 100 1k FREQUENCY 10k
05034-010
0.05 0 -40 -30 -20 -10 0 15 25 35 45 55 65 75 85
100k
TEMPERATURE (C)
Figure 11. AC Power Supply Rejection (VDD = 3.6 V)
3.5 3.0 POSITIVE INL (VDD = 3.8V) 2.5 2.0
INL (LSB)
Figure 14. Zero-Code Error vs. Supply Voltage vs. Temperature
1.5 VDD = 4.5V 1.0 FULL-SCALE ERROR (mA) 0.5 VDD = 3.8V 0 -0.5 -1.0 -1.5 -2.0
POSITIVE INL (VDD = 4.5V)
1.5 1.0 0.5 0 -0.5 -1.0 NEGATIVE INL (VDD = 4.5V) -40 -30 -20 -10 0 15 25 35 45 TEMPERATURE (C) 55 65 75 85 POSITIVE INL (VDD = 3.6V)
NEGATIVE INL (VDD = 3.6V) NEGATIVE INL (VDD = 3.8V)
05034-011
VDD = 3.6V -40 -30 -20 -10 0 15 25 35 45 55 65 75 85
TEMPERATURE (C)
Figure 12. INL vs. Temperature vs. Supply Voltage
1.0 0.8 0.6 0.4
DNL (LSB)
Figure 15. Full-Scale Error vs. Temperature vs. Supply Voltage
1.4 1.3 VDD = 5.5V 1.2 VDD = 4.5V VDD = 3.6V VDD = 2.7V
POSITIVE DNL (VDD = 3.6V)
VOLTAGE (V)
1.1 1.0 0.9 0.8 0.7
POSITIVE DNL (VDD = 4.5V)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 NEGATIVE DNL (VDD = 4.5V) NEGATIVE DNL (VDD = 3.6V) NEGATIVE DNL (VDD = 3.8V) POSITIVE DNL (VDD = 3.8V)
0.6
05034-012
0.5 0.4 -50 -30 -10 10 30 50 70 90
-40 -30 -20 -10
0 15 25 35 45 TEMPERATURE (C)
55
65
75
85
TEMPERATURE (C)
Figure 13. DNL vs. Temperature vs. Supply Voltage
Figure 16. SCL and SDA Logic High Level (VINH) vs. Supply Voltage and Temperature
Rev. 0 | Page 8 of 16
05950-024
05950-014
AD5821
1.4 1.3 1.2 1.1 VOLTAGE (V) VOLTAGE (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -50 -30 -10 10 30 50 70 90 VDD = 3.6V VDD = 5.5V VDD = 4.5V 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 VDD = 2.7V
05950-026
VDD = 5.5V VDD = 4.5V
VDD = 3.6V VDD = 2.7V
05950-027
0.6 0.5 0.4 -50 -30 -10 10 30
50
70
90
TEMPERATURE (C)
TEMPERATURE (C)
Figure 17. SCL and SDA Logic Low Level (VINL) vs. Supply Voltage and Temperature
1.4 1.3 1.2 1.1 VOLTAGE (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -50 -30 -10 10 30 50 70 90
05950-025
Figure 19. DNL vs. XSHUTDOWN Logic Low Level (VINL) vs. Supply Voltage and Temperature
VDD = 5.5V VDD = 4.5V VDD = 3.6V VDD = 2.7V
TEMPERATURE (C)
Figure 18. XSHUTDOWN Logic High Level (VINH) vs. Supply Voltage and Temperature
Rev. 0 | Page 9 of 16
AD5821 TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 6. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output is 0 mA. The zero-code error is always positive in the AD5821 because the output of the DAC cannot go below 0 mA. This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in milliamperes (mA). Gain Error Gain error is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percent of the full-scale range. Gain Error Drift Gain error drift is a measurement of the change in gain error with changes in temperature. It is expressed in LSB/C. Digital-to-Analog Glitch Impulse This is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanoamperes per second (nA-s) and is measured when the digital input code is changed by 1 LSB at the major carry transition. Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. It is specified in nanoamperes per second (nA-s) and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Offset Error Offset error is a measurement of the difference between ISINK (actual) and IOUT (ideal) in the linear region of the transfer function, expressed in milliamperes (mA). Offset error is measured on the AD5821 with Code 16 loaded into the DAC register. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in microvolts per degree Celsius (V/C).
Rev. 0 | Page 10 of 16
AD5821 THEORY OF OPERATION
The AD5821 is a fully integrated, 10-bit digital-to-analog converter (DAC) with 120 mA output current sink capability. It is intended for driving voice coil actuators in applications such as lens autofocus, image stabilization, and optical zoom. The circuit diagram is shown in Figure 20. A 10-bit current output DAC coupled with Resistor R generates the voltage that drives the noninverting input of the operational amplifier. This voltage also appears across the RSENSE resistor and generates the sink current required to drive the voice coil. Resistor R and Resistor RSENSE are interleaved and matched. Therefore, the temperature coefficient and any nonlinearities over temperature are matched, and the output drift over temperature is minimized. Diode D1 is an output protection diode.
XSHUTDOWN REFERENCE POWER-ON RESET SDA SCL I2C SERIAL INTERFACE 10-BIT CURRENT OUTPUT DAC VDD D1 ISINK VDD DGND
When the bus is idle, SCL and SDA are both high. The master device initiates a serial bus operation by generating a start condition, which is defined as a high-to-low transition on the SDA low while SCL is high. The slave device connected to the bus responds to the start condition and shifts in the next eight data bits under control of the serial clock. These eight data bits consist of a 7-bit address, plus a read/write (R/W) bit that is 0 if data is to be written to a device, and 1 if data is to be read from a device. Each slave device on an I2C bus must have a unique address. The address of the AD5821 is 0001100; however, 0001101, 0001110, and 0001111 address the part because the last two bits are unused/don't cares (see Figure 22 and Figure 23). Because the address plus the R/W bit always equals eight bits of data, the write address of the AD5821 is 00011000 (0x18) and the read address is 00011001 (0x19) (see Figure 22 and Figure 23). At the end of the address data, after the R/W bit, the slave device that recognizes its own address responds by generating an acknowledge (ACK) condition. This is defined as the slave device pulling SDA low while SCL is low before the ninth clock pulse and keeping it low during the ninth clock pulse. Upon receiving ACK, the master device can clock data into the AD5821 in a write operation, or it can clock it out in a read operation. Data must change either during the low period of the clock (because SDA transitions during the high period define a start condition, as described previously), or during a stop condition, as described in the Data Format section. I2C data is divided into blocks of eight bits, and the slave generates an ACK at the end of each block. Because the AD5821 requires 10 bits of data, two data-words must be written to it when a write operation occurs, or read from it when a read operation occurs. At the end of a read or write operation, the AD5821 acknowledges the second data byte. The master generates a stop condition, defined as a low-to-high transition on SDA while SCL is high, to end the transaction.
R
AD5821
DGND
RSENSE 3.3
05950-001
AGND
Figure 20. Block Diagram Showing Connection to Voice Coil
SERIAL INTERFACE
The AD5821 is controlled using the industry-standard I2C 2-wire serial protocol. Data can be written to or read from the DAC at data rates of up to 400 kHz. After a read operation, the contents of the input register are reset to all 0s.
I2C BUS OPERATION
An I2C bus operates with one or more master devices that generate the serial clock (SCL) and read and write data on the serial data line (SDA) to and from slave devices such as the AD5821. All devices on an I2C bus have their SDA pin connected to the SDA line and their SCL pin connected to the SCL line of the master device. I2C devices can only pull the bus lines low; pulling high is achieved by pull-up resistors, RP. The value of RP depends on the data rate, bus capacitance, and the maximum load current that the I2C device can sink (3 mA for a standard device).
1.8V
DATA FORMAT
Data is written to the AD5821 high byte first, MSB first, and is shifted into the 16-bit input register. After all data is shifted in, data from the input register is transferred to the DAC register. Because the DAC requires only 10 bits of data, not all bits of the input register data are used. The MSB is reserved for an activehigh, software-controlled, power-down function. Bit 14 is unused; Bit 13 to Bit 4 correspond to the DAC data bits, Bit 9 to Bit 0. Bit 3 to Bit 0 are unused. During a read operation, data is read in the same bit order.
RP
RP
SDA SCL
I2C MASTER DEVICE
I2C SLAVE DEVICE
AD5821
I2C SLAVE DEVICE
Figure 21. Typical I2C Bus
Rev. 0 | Page 11 of 16
05950-016
AD5821
1 SCL 9 1 1 9
SDA START BY MASTER
0
0
0
1
1
1
1
R/W ACK BY AD5821
PD
X
D9
D8
D7
D6
D5
D4 ACK BY AD5821
D3
D2
D1
D0
X
X
X
X ACK BY AD5821 STOP BY MASTER
05950-017
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 MOST SIGNIFICANT DATA BYTE
FRAME 3 LEAST SIGNIFICANT DATA BYTE
Figure 22. Write Operation
1 SCL
9
1
1
9
SDA START BY MASTER
0
0
0
1
1
1
1
R/W ACK BY AD5821
PD
X
D9
D8
D7
D6
D5
D4 ACK BY AD5821
D3
D2
D1
D0
X
X
X
X ACK BY AD5821 STOP BY MASTER
05950-018
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 MOST SIGNIFICANT DATA BYTE
FRAME 3 LEAST SIGNIFICANT DATA BYTE
Figure 23. Read Operation
Table 6. Data Format 1
Serial Data-Words Serial Data Bits Input Register Function
1
High Byte SD7 R15 XSHUTDOWN
SD6 R14 X
SD5 R13 D9
SD4 R12 D8
SD3 R11 D7
SD2 R10 D6
SD1 R9 D5
SD0 R8 D4
Low Byte SD7 SD6 R7 R6 D3 D2
SD5 R5 D1
SD4 R4 D0
SD3 R3 X
SD2 R2 X
SD1 R1 X
SD0 R0 X
XSHUTDOWN = soft power-down; X = unused/don't care; and D9 to D0 = DAC data.
VBATTERY
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in an application, it is beneficial to consider power supply and ground return layout on the PCB. The PCB for the AD5821 should have separate analog and digital power supply sections. Where shared AGND and DGND is necessary, the connection of grounds should be made at only one point, as close as possible to the AD5821. Special attention should be paid to the layout of the AGND return path and, and it should be tracked between the voice coil motor and ISINK to minimize any series resistance. Figure 24 shows the output current sink of the AD5821 and illustrates the importance of reducing the effective series impedance of AGND and the track resistance between the motor and ISINK. The voice coil is modeled as Inductor LC and Resistor RC. The current through the voice coil is effectively a dc current that results in a voltage drop, VC, when the AD5821 is sinking current. The effect of any series inductance is minimal.
VOICE COIL VDD LC RC VCOIL
DGND
AD5821
RT ISINK
TRACE RESISTANCE
SDA SCL XSHUTDOWN DGND RG LG RSENSE
Q1 VDROP
R
AGND
GROUND RETURN
05950-019
Figure 24. Effect of PCB Trace Resistance and Inductance
Rev. 0 | Page 12 of 16
AD5821
When sinking the maximum current of 120 mA, the maximum voltage drop allowed across RSENSE is 400 mV, and the minimum drain to source voltage of Q1 is 200 mV. This means that the AD5821 output has a compliance voltage of 600 mV. If VDROP falls below 600 mV, the output transistor, Q1, can no longer operate properly and ISINK may not be maintained as a constant. When sinking 90 mA, the maximum voltage drop allowed across RSENSE is 300 mV, and the minimum drain to source voltage of Q1 is 180 mV. This means that the AD5821 output has a compliance voltage of 480 mV. If VDROP falls below 480 mV, the output transistor, Q1, can no longer operate properly and ISINK may not be maintained as a constant. As ISINK decreases, the voltage required across the transistor, Q1, also decreases and, therefore, lower supplies can be used with the voice coil motor. As the current increases to 120 mA through the voice coil, VC increases. VDROP decreases and eventually approaches the minimum specified compliance voltage of 600 mV (or 480 mV, if ISINK = 90 mA). The ground return path is modeled by the components RG and LG. The track resistance between the voice coil and the AD5821 is modeled as RT. The inductive effects of LG influence RSENSE and RC equally, and because the current is maintained as a constant, it is not as critical as the purely resistive component of the ground return path. When the maximum sink current is flowing through the motor, the resistive elements, RT and RG, may have an impact on the voltage headroom of Q1 and could, in turn, limit the maximum value of RC because of voltage compliance. For example, if VBATTERY = 3.6 V RG = 0.5 RT = 0.5 ISINK = 120 mA VDROP = 600 mV (the compliance voltage) Then the largest value of resistance of the voice coil, RC, is
RC = VBAT - [VDROP + ( I SINK x RT ) + ( I SINK x RG )] = I SINK
Using another example, if VBATTERY = 3.6 V RG = 0.5 RT = 0.5 ISINK = 90 mA VDROP = 480 mV (the compliance voltage specification at 90 mA) Then the largest value of resistance of the voice coil, RC, is
RC = VBAT - [VDROP + ( I SINK x RT ) + ( I SINK x RG )] = I SINK
3.6 V - [480 mV + 2 x (90 mA x 0.5 )] 90 mA
= 33.66
For this reason, it is important to minimize any series impedance on both the ground return path and interconnect between the AD5821 and the motor. It is also important to note that for lower values of ISINK, the compliance voltage of the output stage also decreases. This decrease allows the user to either use voice coil motors with high resistance values or decrease the power supply voltage on the voice coil motor. The compliance voltage decreases as the ISINK current decreases. The power supply of the AD5821, or the regulator used to supply the AD5821, should be decoupled. Best practice power supply decoupling recommends that the power supply be decoupled with a 10 F capacitor. Ideally, this 10 F capacitor should be of a tantalum bead type. However, if the power supply or regulator supply is well regulated and clean, such decoupling may not be required. The AD5821 should be decoupled locally with a 0.1 F ceramic capacitor, and this 0.1 F capacitor should be located as close as possible to the VDD pin. The 0.1 F capacitor should be ceramic with a low effective series resistance and effective series inductance. The 0.1 F capacitor provides a low impedance path to ground for high transient currents. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, they should run at right angles to each other to reduce feedthrough effects through the board. The best technique is to use a multilayer board with ground and power planes, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
3.6 V - [600 mV + 2 x (120 mA x 0.5 )] 120 mA
= 24
Rev. 0 | Page 13 of 16
AD5821 APPLICATIONS INFORMATION
The AD5821 is designed to drive both spring-preloaded and nonspring linear motors used in applications such as lens autofocus, image stabilization, or optical zoom. The operation principle of the spring-preloaded motor is that the lens position is controlled by the balancing of a voice coil and spring. Figure 25 shows the transfer curve of a typical spring-preloaded linear motor for autofocus. The key points of this transfer function are displacement or stroke, which is the actual distance the lens moves in millimeters (mm) and the current through the motor, measured in milliamps (mA). A start current is associated with spring-preloaded linear motors, which is a threshold current that must be exceeded for any displacement in the lens to occur. The start current is usually 20 mA or greater; the rated stroke or displacement is usually 0.25 mm to 0.4 mm; and the slope of the transfer curve is approximately 10 m/mA or less. The AD5821 is designed to sink up to 120 mA, which is more than adequate for available commercial linear motors or voice coils. Another factor that makes the AD5821 the ideal solution for these applications is the monotonicity of the device, ensuring that lens positioning is repeatable for the application of a given digital word. Figure 26 shows a typical application circuit for the AD5821.
VDD 0.1F
6 2
0.5
0.4
STROKE (mm)
0.3
0.2 START CURRENT 0.1
10
20
30
40
50
60
70
80
90 100 110 120
SINK CURRENT (mA)
Figure 25. Spring-Preloaded Voice Coil Stroke vs. Sink Current
VCC
VDD XSHUTDOWN RP RP
1
REFERENCE
POWER-ON RESET
VOICE COIL
SDA SCL
3 4
I2C SERIAL INTERFACE
10-BIT CURRENT OUTPUT DAC
D1
8
ISINK
I2C MASTER DEVICE
I2C SLAVE DEVICE
5
R
RSENSE
AD5821
7
VDD 10F +
VCC
05950-028
0.1F
10F
+
Figure 26. Typical Application Circuit
Rev. 0 | Page 14 of 16
05950-029
AD5821 OUTLINE DIMENSIONS
1.575 1.515 1.455 0.65 0.59 0.53 SEATING PLANE 0.36 0.32 0.28
3 2 1 A
BALL 1 IDENTIFIER
1.750 1.690 1.630
B
0.50 BSC BALL PITCH TOP VIEW
(BALL SIDE DOWN)
C
Figure 27. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5821BCBZ-REEL7 1 AD5821BCBZ-REEL1 AD5821-WAFER AD5821D-WAFER EVAL-AD5821EBZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 9-Ball Wafer Level Chip Scale Package (WLCSP) 9-Ball Wafer Level Chip Scale Package (WLCSP) Bare Die Wafer Bare Die Wafer on Film Evaluation Board
Package Option CB-9-1 CB-9-1
Branding D82 D82
Z = Pb-free part.
Rev. 0 | Page 15 of 16
110405-0
0.28 0.24 0.20
BOTTOM VIEW
(BALL SIDE UP)
AD5821 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05950-0-1/07(0)
T T
Rev. 0 | Page 16 of 16

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